Field of the Invention
The present invention relates to a semiconductor integrated circuit and a control method of a semiconductor integrated circuit.
Description of the Related Art
Generally, an image forming apparatus that operates by switching between a power-saving mode and a normal power mode controls power supply to a semiconductor integrated circuit mounted thereon in accordance with the transition of the power mode. By the configuration such as this, suppression of power consumption as a whole of the image forming apparatus is attempted.
A semiconductor integrated circuit includes a logic circuit that performs arithmetic operation processing and a static memory (SRAM) circuit that is used as a storage area of data. The semiconductor integrated circuit disclosed in Japanese Patent Laid-Open No. 2014-149910 supplies minimum power necessary to hold data in the SRAM circuit while shutting off power supply to the logic circuit at the time of standby. Due to the configuration such as this, it is possible for the semiconductor integrated circuit disclosed in Japanese Patent Laid-Open No. 2014-149910 to make an attempt to save power at the time of standby while holding data in the SRAM. In the semiconductor integrated circuit such as this, the state where minimum power necessary to hold data is supplied to the SRAM is called a resume standby mode (hereinafter, described as “RS mode”).